Circuits which perform addition by 1, known as incrementers, are widely used in microprocessors due to the sequential nature of instruction generation and execution. Implementation in dynamic logic offers considerable speed advantages. However, adders and incrementers use both true and complement signals. In dynamic logic schemes, if both true and complement ("dual rail") signals are required, they usually have to be generated in parallel from the preceding latch, thereby consuming twice the area of and dissipating more power than single-rail logic. Therefore an optimized incrementer can provide a reduction in area and in power dissipated across an entire microprocessor chip.
In an incrementer, as in an adder, the critical path consists of the calculation of the carry signals. These are usually calculated by the use of an AND tree, which can be 64 high in state of the art 64-bit microprocessors. This limits the achievable speed.